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New Features
- Added new experimental memory test as Test 14 [DMA test]. This test exercises the disk controller's DMA hardware to perform memory access, bypassing the CPU. The motivation for this test came from discovering a defective RAM module that did not produce errors when accessed via the CPU, but failed when files were read from disk via DMA. As this test is experimental, it shall be disabled by default.
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DIMM (Pro edition)/chip-level (Site Edition) error detection on limited number of hardware platforms. This includes mid-test error reporting, graphical UI summary report on test completion and per-DIMM/chip error count table in the HTML report.
- Added new config file parameter, 'CPUMAP', to specify the DRAM chip labeling map. By default, DRAM chips are labeled consecutively starting from U0 (eg. U0, U1,..., U15)
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Fixes/Enhancements
- Log file name now includes the timestamp
- Added new blacklist flag 'DISABLE_CPUINFO' for disabling CPU info collection
- Fixed 'MAXCPUS' config file parameter not being applied
- Fixed hammer test incorrectly running in single-sided mode in Free version
- Fixed clock speed measurement failure for ARM chipsets due to cycle count register not being enabled
- Fixed detection of MAC address used as unique ID for PXE boot
- Added support for reporting IBECC errors
- Fixed bug in reading ECC error count registers for various Intel/AMD Ryzen chipsets
- Fixed reading ECC error status register for Intel Tiger Lake-H and Alder Lake chipsets
- Fixed ECC detection on Intel Ice Lake-SP chipsets
- Added ECC detection support for multi-socket Intel Ice Lake-SP chipsets
- Fixed ECC support for Intel Rocket Lake chipset variant
- Added ECC support for AMD Ryzen Zen 3 50h-5fh chipset
- Fixed ECC support for AMD Ryzen Zen 2 chipsets with 2 memory channels
- Fixed ECC error false positives on Intel Atom C2000 chipsets
- Added support for retrieving Intel Ice Lake-SP CPU info
- Added support for retrieving Intel Ice Lake-SP RAM SPD data
- Added support for retrieving Intel Ice Lake-SP RAM temperature data
- Added SMBus (SPD) support for Intel Alder Lake-P
- Enable SMBus on Intel 801-based chipsets if disabled
- Fixed detection of SPD modules on systems with > 8 SMBus controllers (eg. quad socket systems)
- Fixed bug in mapping SPD module index to SMBIOS slot index
- Fixed detection of SPD slot for systems with soldered and removable DIMMs
- Fixed incorrect calculation of DDR5 transfer bandwidth
- Fixed DDR5 memory type in SMBIOS not being correctly parsed
- Fixed identification of data partition in USB flash drive
- Create 'Benchmark' directory to store RAM benchmark results if it does not already exist
- Updated blacklist
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